Flip-Flop Timing Parameters and Circuit Behavior Analysis
Question 1
Which of the following flip-flop timing parameters indicates the time it takes a Q output to respond to an
input?
Question 1 options:
tw(1), tw(h)
fmax
ts, th
tphl, tplh
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Question 2
Asynchronous flip-flop preset and clear inputs generally:
Question 2 options:
cause the outputs to change states depending on the SR, JK, or similar controlling
inputs.
cause the outputs to change states as soon as the input clock makes the desired
transition.
clear the inputs so the flip-flop can start over.
act as manual overrides that cause the outputs to change states regardless of the
inputs or clock transitions.
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Question 3
The setup time of a clocked flip-flop is:
Question 3 options:
the maximum amount of time that an output must remain stable after an active
clock transition.
the minimum amount of time that an output must remain stable before an active
clock transition.
the minimum amount of time that an input must remain stable before an active
clock transition.
the minimum amount of time that an input must remain stable after an active clock
transition.
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Question 4
The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle
indicates:
Question 4 options:
the FF is level active and can only change states when the CLOCK = 1.

the FF is edge-triggered and can only change states when the clock goes from 1 to
0.
the FF is an active LOW device and can only change states when the CLOCK = 0.
the FF is edge-triggered and can only change states when the clock goes 0 to 1.
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Question 5
A negative-edge-triggered J-K flip-flop is presently in the CLEAR state. Which of the following input
conditions will cause it to change states?
Note:
PGT: Clock transition from '0' to '1'
NGT: Clock transition from '1' to '0'
Question 5 options:
CLK = PGT, J = 1, and K = 0
CLK = PGT, J = O, and K = 1
CLK = NGT, J = O, and K = 1
CLK = NGT, J = 1, and K = 0
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Question 6
The difference between a D-latch and an edge-triggered D-type flip-flop is that the latch:
Question 6 options:
always "latches" the Q output to the D input regardless of other inputs.
is controlled by the logic level at its ENABLE input rather than a CLK transition.
always "latches" the Q output to the complement of the D input regardless of other
inputs.
triggers on either the rising or falling edge of an ENABLE signal rather than the
CLK input logic level.
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Question 7

The preset and clear inputs to a J-K flip-flop are HIGH (1). Which of the following is true?
Question 7 options:
The Q output is immediately set to 1.
The flip-flop is free to respond to its J, K, and clock inputs.
The Q output is in an ambiguous state.
The Q output is immediately cleared.
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Question 8
What is one disadvantage of an R-S flip-flop?
Question 8 options:
It has no Enable input.
It has only a single output.
It has an invalid state.
It has no CLOCK input.
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Question 9
If both inputs of an S-R flip-flop are low, what will happen when the clock goes high?
Question 9 options:
An invalid state will exist.
No change will occur in the output.
The output will reset.
The output will toggle.
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Flip-Flop Timing Parameters and Circuit Behavior Analysis

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